The present invention relates to nonvolatile memory devices and, more particularly, to a method of manufacturing a nonvolatile memory device, which method can reduce the interference capacitance between neighboring word lines.
Information stored in the cells of a nonvolatile memory device is not lost when the power is off. The nonvolatile memory device includes a thin tunnel oxide layer, a floating gate, a control gate, and an insulator for isolating the two gates, which are formed over a silicon substrate.
FIG. 1 is a perspective view of a conventional NAND flash memory device.
Referring to FIG. 1, isolation layers 110 are formed by a Shallow Trench Isolation (STI) process, and define a field region and an active region. A tunnel oxide layer 120 is formed over a semiconductor substrate 100 in which the isolation layers 110 are formed. Floating gates 130 are formed on the tunnel oxide layer 120 to overlap with the edges of the isolation layers 110. Each floating gate 130 has a first conductive layer 130a and a second conductive layer 130b laminated thereon.
An Oxide-Nitride-Oxide (ONO) dielectric layer 140 and a control gate 150 are laminated on the floating gates 130, and over the isolation layer 110 between the floating gates 130.
At this time, a distance between neighboring word lines is reduced, and an opposing area (gate to gate) between neighboring floating gates between the respective word lines is increased, resulting in an interference capacitance CFGY. The interference phenomenon becomes substantial due to the interference capacitance, making normal cell operation difficult.
FIG. 2 is a graph illustrating the difference in the distributions of a word line-based program threshold voltage Vth in the NAND flash memory device of FIG. 1.
From FIG. 2, the interference phenomenon between neighboring word lines for the outermost gate line (i.e., WL31) is relatively small and the threshold voltage distributions are therefore good for distributions of the word line-based program threshold voltage Vth in NAND flash memory having 32 strings. However, distributions of the threshold voltage Vth are very large due to the interference phenomenon in the X- and Y-directions, except for WL31.
Because it is preferable for NAND flash memory to have small distributions of the threshold voltage Vth, it is important to minimize the interference phenomenon as well as to secure the coupling ratio.